There has been known a display device that includes a memory circuit (hereinafter referred to as a pixel memory) in each pixel and stores image data in the pixel memory so as to display a static image with low power consumption without being continuously supplied with image data from the outside. The power consumption is reduced by e.g., (i) an amount of power for charging and discharging, by image data, data signal lines for supplying the image data to the pixels and (ii) an amount of power for transmitting image data from the outside of a panel to a driver. The amount (i) is reduced because such the charge or discharge is no longer necessary once the image data is written into the pixel memory, and the amount (ii) is reduced because such the transmission is no longer necessary once the image data is written into the pixel memory.
SRAM-based and DRAM-based pixel memories have been developed. A pixel voltage of a display device having the SRAM-based or DRAM-based pixel memory is digital. Therefore, such the display device hardly causes crosstalk, and has excellent display quality.
FIG. 14 shows a configuration of a display device including such a pixel memory described in Patent Literature 1.
The display device includes an X address scanning line driver 18, a digital data driver 19, and an analog data driver 20, and can perform a digital data image display mode and an analog data image display mode separately.
The following will describe the digital data image display mode. An X address signal line 4-n (n is a positive integer) connected with a pixel where image data is to be written is selected. Then, from its corresponding first display control line 1-n, a digital data signal is written into a digital memory element 100 including a NAND circuit 11 and a clocked inverter element 13, through a first switch element 8 of the pixel. At this time, the digital memory element 100 is made active via a display mode control line 15.
An input of the digital memory element 100 is connected to a second switch element 9, and an output of the digital memory element 100 is connected to a third switch element 10. Therefore, depending on High or Low of the digital data signal, either the second switch element 9 or the third switch element 10 becomes conductive. A white display reference voltage is supplied to one of a second display control line 2-n and a third display control line 3, and a black display reference voltage is supplied to the other one of the second display control line 2-n and the third display control line 3. Depending on the switch element which has become conductive, the second switch element 9 or the third switch element 10, the white display voltage or black display voltage is selected, and then is applied to a liquid crystal cell 6. The liquid crystal cell 6 maintains a display state caused by the digital data signal stored in the digital memory element 100, until the first switch element 8 becomes conductive again and another digital data signal is written into the digital memory element 100.
Patent Literature 1
Japanese Patent Application Publication, Tokukai, No. 2003-177717 A (Publication Date: Jun. 27, 2003)
Patent Literature 2
Japanese Patent Application Publication, Tokukaisho, No. 58-23091 A (Publication Date: Feb. 10, 1983)
Patent Literature 3
Japanese Patent Application Publication, Tokukai, No. 2007-286237 A (Publication Date: Nov. 1, 2007)